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I have a makefile from an example project, and it unfortunately forces a re-build when any single file in the project changes. I do not have a lot of experience with makefiles, so I'm not sure how to solve this problem.
The makefile defines the files to compile as a single variable SRCS
like shown below. Of course, there are about 40 files in this list, in quite a few different directories.
SRCS = \
../../src/file1.c \
../../src/file2.c
Then later it defines the build rules for each .o
file generated from each .c
file.
$(OBJ_PATH)/%.o: $(SRCS)
$(CC) $(FLAGS) $(filter %/$(subst .o,.c,$(notdir $@)), $(SRCS)) -o $@
According to make running with the -d
option, all of the object files must be compiled again when a single .c
file changes because $(SRCS)
is defined as a dependency above.
How can I change this so if a single file changes only the 1 .o
file must be compiled again?
asked 2 mins ago
Makefile doesn't permit incremental build
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